The invention relates to a testing device for testing a memory, in particular a random access semiconductor memory having a multiplicity of memory cells associated with bit lines that can be connected to input/output lines leading out of the memory by a drive circuit. The testing device tests the memory by performing a plurality of individual tests in accordance with a test program. The invention also relates to a method for testing a memory and to a circuit arrangement having a multiplicity of circuits that will be tested, that are formed on a common substrate, and that are separated in a following fabrication step.
As memory cell arrays in semiconductor memories become larger and larger with generation changes taking place at increasing speed, memory capacity is expected to approximately quadruple very three years (for example from the 64 Mbit DRAM generation to the 256 Mbit DRAM generation). It is essential to test memory cells in semiconductor memories because under certain circumstances a single defective memory cell can lead to the total failure of the entire semiconductor memory. For this reason, in most semiconductor memories, redundant memory cells are provided which are addressed instead of the defective memory cells. However, it is necessary to test the operational capability of the entire memory, i.e. of each semiconductor memory cell, to be able to replace the memory cells that are identified as faulty with redundant memory cells if appropriate. Hitherto, testers were used, which make contact with the semiconductor chips while they are still in the composite wafer by placing small needles on the contact areas. There are also testers that make contact with the semiconductor chips when they are already housed or wired. After the tester makes contact with the semiconductor chips, all the memory cells of the memory cell array are tested. The addresses of the defective memory cells are stored externally (that is to say in the tester) and are used for redundancy evaluation after testing the operational capability. In this evaluation, redundant memory cells are assigned to the addresses of the defective memory cells.
Given the currently achieved sizes of memory cell arrays with storage capacities of 256 Mbit or 1 Gbit, testing the memory cells entails considerable costs that are proportional to the size of the memory and are thus related exponentially to the generation of the memory chip. The testing procedure requires greater time for each semiconductor memory produced. For the imminent 1 Gbit generation, it is estimated that the testing costs make up 30% of the entire production costs.
Because the hardware of the expensive testers has to be adapted with each new generation, which again signifies significant expenditure, attempts are being made to reduce the necessary tests to a minimum. Carrying out the tests on several chips simultaneously cannot be expanded any more using the customary testing of up to 64 memories because this approach is limited by the number of contact needles of the tester that can be placed on the chip. Even with a conceivable reduction of the contact needles that are required for the test and that are to be placed on the chip, the entire memory cell array would have to be tested by the tester on a cell-by-cell basis.
The data that has been acquired by the test, relating to the position and/or addresses of the defective memory cells, is evaluated after the test by the hardware and the software of the tester or by a further external device. Here, a redundancy analysis is carried out which assigns redundant memory cells to the addresses of the defective memory cells. This assignment data is subsequently buffered or fed directly to an element that xe2x80x9cwiresxe2x80x9d the assignment onto the chip. This can be done using a laser beam that burns away tracks, using fuses or anti-fuses, or using other suitable means.
The test program is generally contained in the external tester in the form of a fixed circuit or is produced by means of programmable units at great cost. Changing the test program or the devices that carry out the test leads to very cost-intensive delays in mass production, which often entails a loss of time that can not be made up.
It is accordingly an object of the invention to provide a testing device, a circuit configuration including a plurality of circuits that will be tested, and a method for testing a memory which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a testing device that can be used universally, i.e. that does not require any structural changes when used with various memory sizes (that is to say is independent of the size of the memory arrays to be tested) or memory types. It is an object to enable the testing device to be quickly adapted to a changing test program without having to perform structural interventions. It is also an object of the invention to reduce the test duration.
With the foregoing and other objects in view there is provided, in accordance with the invention, a testing device in combination with a substrate having a memory that will be tested. The memory includes a plurality of memory cells and the memory stores a test program. The memory is formed either in the substrate or on the substrate. The testing device includes an interpreter element that operates and tests the memory in accordance with the test program that is stored in the memory.
A testing device that operates in accordance with a test program is provided. The test program command codes of the testing device are stored in the untested memory cell array of the memory chip that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device per se no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program which is suitable for the respective chip type is stored as a variable code on the respective memory that will be tested. It is thus also possible to test various memory chip types with the same testing device. Rapid adaptation of the test programs for the memory chips is also possible without necessitating intervention in the testing device. It is thus no longer necessary to perform time-consuming changing of the testers and/or of the programs that control the testers or to store the programs again in the case of different memory types. Additionally, it is no longer necessary to change the circuits of the memory chips. The exponential growth in the testing time using the expensive testers and the associated costs are prevented. As a result of the new approach of the individually programmable and cost-effective testing device, all of the tests that relate to the memory cell array can also be carried out in a more detailed way. This constitutes a significant improvement in that the faulty chips or their fault sources can be analyzed more precisely. The testing device can be used flexibly and can be quickly adapted to a new test program without having to make structural changes to the circuits of the memory; this enables the overall time that is necessary for the testing to be reduced.
In accordance with an added feature of the invention, the testing device is formed on or in the substrate. As a result, the formation of external contacts using contact needles that would be placed on the substrate of the memory is advantageously no longer necessary. This minimizes the use of external equipment, or makes it superfluous, and testing while already in the composite wafer is made possible.
In accordance with an additional feature of the invention, a plurality of identical or independent memories are formed in the substrate. These memories will be separated after the test is concluded, and if appropriate, after action in accordance with the results of these tests have been taken. The advantage is that the wafer on or in which the individual memory chips are formed is significantly easier to handle than a multiplicity of individual memory chips, and that parallel testing of all of the chips fabricated on the wafer is simultaneously possible.
In accordance with another feature of the invention, each individual memory has a separate testing device that is formed on or in the substrate. As a result, even different types of memories can be formed on a single wafer and/or different test programs can be used for the individual memories.
In accordance with a further feature of the invention, all of the memories are associated with a single common testing device. This minimizes the necessary chip area and the substrate area on the individual memory chips is not wasted on the testing device, which is required only once.
In accordance with a further added feature of the invention, the interpreter element has a control part which, in accordance with respective individual test instructions of the test program, writes a specific test data pattern to one or more memory cells of the memory cell array of the memory undergoing testing. The interpreter element makes this test data pattern available as the expected data. After this, in a further advantageous embodiment of the invention, a comparator device is provided which compares the data read out of the memory cells of the tested memory with the expected data which is made available. The interpreter element supplies a result in the event of an inequality. Consequently, effective and simple functional testing of the individual memory cells is achieved.
In accordance with a further additional feature of the invention, a test instruction reading device reads the individual test instructions of the test program out from the tested memory cell array and makes the individual test instruction available to the control part. As a result, the control part can operate independently of the need to extract individual test instructions from the tested memory cell array.
After this, one or more registers are advantageously provided, which buffer the individual test instructions. The individual test instructions are fetched in succession from the registers by the control part. This provides an advantage in that the control part can operate independently from the speed of the test instruction reading device and from the speed that the individual test instructions are processed.
In accordance with yet an added feature of the invention, a writing device is provided which writes the results of the comparator device into a results memory. After this, one or more registers are advantageously provided which buffer the individual results. The results are read out from the registers by the writing device. The advantage achieved in this way is that the writing device can operate independently from the speeds of the comparator device and the storage of the results.
In accordance with yet an additional feature of the invention, the results memory is embodied as an external test memory or as a test memory formed on the substrate. In this way, the results can be stored and evaluated at a later time for a redundancy analysis.
In accordance with yet another feature of the invention, the results memory is formed by the memory cells of the tested memory. In this way, the space that would be required by an additional test memory and/or by contacting means for transferring the results into an external memory on the substrate becomes free. After this, the writing device is advantageously embodied such that writing the results of the comparator device into the memory cells of the tested memory takes place in a redundant fashion, that is to say in a way which is tolerant of faulty memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration that includes a substrate having a plurality of circuits formed thereon. The substrate has intermediate spaces formed between the plurality of the circuits and separating the plurality of the circuits. The substrate has feedlines formed in the intermediate spaces and connected to the plurality of the circuits. Each one of the plurality of the circuits stores a test program. The circuit configuration also includes a testing device connected to at least one of the feedlines. The testing device includes an interpreter element that operates and tests at least one of the plurality of the circuits in accordance with the test program that is stored in that one of the plurality of the circuits.
In other words, the circuit arrangement has a plurality of circuits, in particular memories, formed on a common substrate. The circuits have an intermediate space between them in order to permit them to be separated. Feedlines which connect the individual circuits to one another and/or to one or more additional circuits are formed in the intermediate spaces. As a result, electrical contact between the circuits, which are still located in the semiconductor assembly on the common substrate, is made possible such that the required line routes do not take up space on the substrate which can be used for the circuits. The feedlines are formed in the region of the substrate which is lost when the circuits are separated, and therefore cannot be used for the circuits.
In accordance with an added feature of the invention, the substrate has an edge region; and the testing device is formed either in the intermediate spaces or the edge region.
In accordance with an additional feature of the invention, there is provided, a test memory for recording test data acquired by the testing device; and a program memory for storing instructions of a program used by the testing device. The test memory is connected by the feedlines to either the testing device or least one of the plurality of the circuits. The program memory is connected by the feedlines to either the testing device or at least one of the plurality of the circuits.
In accordance with another feature of the invention, the test memory is formed either in one of the intermediate spaces or the edge region. The program memory is formed either in one of the intermediate spaces or in the edge region.
In accordance with a further feature of the invention, the substrate includes contact areas for electrically contacting the plurality of the circuits. The contact areas are formed either in one of the intermediate spaces or in the edge region.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for testing a memory. The method includes steps of: forming a program memory from memory cells of a memory that will be tested; reading at least one individual test instruction out of the program memory; using a control part to interpret the test instruction; writing a test data pattern, defined by at least one individual test instruction, to memory cells of a memory cell array that will be tested; reading memory states of the memory cells of the memory cell array to which the test data pattern had been written; comparing the memory states with expected data that is predefined by the test data pattern; if the memory states are not equal to the expected data, then storing addresses of the memory cells of the memory cell array into a results memory; and reading at least one additional individual test instruction from the program memory.
The program memory and/or the results memory are preferably embodied by the memory cells of the tested memory.
In accordance with an added mode of the invention, a plurality of memories are tested when they still are located in the substrate assembly (wafer assembly). As a result, the memories are tested particularly effectively and cost-effectively because the testing takes place before the individual memories are separated.
In accordance with an additional mode of the invention, the test program containing the individual test instructions is stored in the memory/memories that will be tested before the beginning of the test.
In accordance with a concomitant mode of the invention, the addresses of the faulty memory cells are stored redundantly and/or the individual test instructions are read out redundantly. This makes it possible to store, and to subsequently read out, the test program and/or the results such that faulty memory cells of the tested memory can be tolerated. These results are in the form of addresses of the faulty memory cells.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a testing device for testing a memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.